Programming FPGAs with MaxJ

Programming FPGAs with MaxJ

organized for

Researchers and Students (PhD, MSc)

September 23 & 24, 2019

Field Programmable Gate Arrays (FPGAs) are reconfigurable chips, which facilitate direct implementation of algorithms (or their data intensive parts) as hardware circuits. This enables the development of application specific hardware accelerators, delivering high throughput, low energy and constant latency to solution and very fine grain control over all basic arithmetic operations, their sizes and properties. FPGA based systems enable highly customised, application specific dataformats for each individual fixed and floating point variable but is not limited to the above two types. As a result, FPGA accelerators have seen a rapid adoption by both Industry and Academia especially in the context of high performance computing. The efficient design for FPGAs based systems, however, combines three distinct knowledge areas: i) the application specific system architecture to maximally utilise all available compute and interconnect capabilities; ii) dedicated programming tools and languages; and iii) FPGA specific design and programming methodologies.

Course goal: In this 2-day course we will explain the basic principles and some advanced topics of FPGA programming with MaxJ, which is a Java based programming language used to leverage the dataflow abstraction for high performance computing. The programmer describes a custom dataflow graph which is translated to a hardware circuit. The MaxJ toolchain provides an easy to use framework aimed at domain experts and not hardware engineers. After this course you will be able to successfully benefit from dataflow computing to your own work.

Preliminaries: A rudimentary understanding of programming languages like C++ or Java is ideal. Some interest in computer architecture, computer arithmetic and numeric analysis is of additional advantage. Please bring your own laptop with pre-installed VirtualBox (https://www.virtualbox.org) so that you can run and experiment with the provided hands-on examples.

Teachers: Prof Georgi Gaydadjiev (GG), Mr Nils Voss (NV) from Maxeler IoT-Labs BV and Dr Christos Strydis (CS) of the Neuroscience department of the Erasmus Medical Centre will teach this course

Costs: The course is free for DCSE members. TU Delft staff and students pay € 50/100 for attending one/two-day(s) respectively. The fee for other participants is € 200/350. Lunch, refreshments, lecture materials are included.

Location: EEMCS building 28, Penguin Lab (E0.380), van Mourik Broekmanweg 6, Delft.

Registration: at https://www.aanmelder.nl/fpgacourse/subscribe

Kind regards,

The organization committee